This invention relates, in general, to semiconductor memory devices and more particularly, to electrically alterable, nonvolatile floating gate memory devices.
The microprocessor based systems, as well as the related arts, have long required electrically alterable read only memory (EAROM) elements that were nonvolatile and many such devices have, to some extent, filled this need. However, as the computer arts have become more complex in nature and have required high speeds and greater capacity there now exists the need for a high density memory device that may be easily programmed or "written" and, as the occasion arises, to reprogram ("erase" and "rewrite") the device in the field. To this end, devices are presently available to the design engineers that exhibit nonvolatile characteristics but, as will be discussed, they have inherent shortcomings that are overcome by the subject invention.
One such device resides in the family of Floating Gate Avalanche Metal Oxide Semiconductor (FAMOS) devices. The advantage of this type of device resides in the fact that it is independent of any outside current to maintain the stored information in the event power is lost or interrupted. Since these devices are independent of any outside power there is also no need to refresh the device which feature results in a significant savings in power.
The floating gate family of devices usually has source and drain regions of a given conductivity type, formed in a substrate of the opposite conductivity type, at the surface thereof. Between the source and drain regions, and on the surface of the substrate, a gate structure is formed by first applying a thin insulating layer followed by a conductive layer (the floating gate) followed by a second insulating layer in order to completely surround the floating gate and insulate it from the remainder of the device. A second conductive layer (usually referred to as the control gate) is formed over the second insulating layer (in the region of the floating gate) to complete the gate structure. One example of such a device is exemplified in U.S. Pat. No. 3,500,142 which issued to D. Kahng on Mar. 10, 1970.
The major drawback of this prior art device resides in the fact that high fields are required to produce the necessary avalanche breakdown in order for charge to be placed on the floating gate. Further, to erase charge placed on the floating gate, the entire device must be provided with a transparent window so that the chip may be flooded with energy in the ultra violet or x-ray portion of the spectrum. Thus, it is extremely difficult to erase a single "word" without erasing all the charge on the device then requiring that the entire chip be completely reprogrammed. Further, the erasing step required an extremely long period of exposure time, of the order of about 30 to 45 minutes, with the device or chip removed from the equipment.
In the recent years, the art has progressed to the point where nonvolatile, floating gate read only memory devices have been produced which are electrically alterable. One such memory cell has been described in detail in an article entitled "16K -EE.sup.2 PROM Relies on Tunneling for Byte-Erasable Program Storage" by W. S. Johnson, et al., ELECTRONICS, Feb. 28, 1980, pp. 113-117. In this article the authors describe a "Floating-Gate Tunnel Oxide" structure wherein a cell using a polycrystalline silicon (polysilicon) floating gate structure has its gate member charged with electrons (or holes) through thin oxide layer positioned between the floating gate and the substrate by means of the Fowler-Nordheim tunneling mechanism. An elevation view of a typical device is described, and shown in FIG. 1 of the article, wherein the floating gate member represents the first polysilicon level. By using this type of structure (a structure wherein the first level polysilicon represents the floating gate since it is closest to the substrate, and is covered by a second polysilicon level) an excessively high floating gate-to-substrate capacitance is produced. However, acceptably low "write" and "erase" operations can only be achieved when most of the applied voltage appears across the tunnel region which requires that the floating gate-to-control gate (second polysilicon level) capacitance be larger than the floating gate-to-substrate capacitance. Further, to achieve the required distribution of capacitance to produce the acceptable "write" and "erase" characteristics, the prior art has resorted to extending both the first and second polysilicon levels over the adjacent field oxide to obtain the additional capacitance. The net result is an undesirably large cell wherein large areas of field oxide must be utilized to achieve the necessary capacitance.
In a recent application, filed in the U.S. Patent and Trademark Office by the same applicants on Feb. 18, 1983 Ser. No. 467,463 entitled "AN ELECTRICALLY ALTERABLE, NONVOLATILE FLOATING GATE MEMORY DEVICE", and assigned to the same assignee as the subject application, we described a novel configuration of floating gate memory device wherein: EQU C.sub.2 &lt;C.sub.3 &gt;C.sub.1 and (1) EQU C.sub.3 =xC.sub.2 =yC.sub.1 ( 1a)
where:
C.sub.1 =The floating gate-to-substrate capacitance;
C.sub.2 =The first conductive layer-to-floating gate capacitance; and
C.sub.3 =The second conductive layer-to-floating gate capacitance.
X&gt;1 and Y&gt;1.
In the example given when, for example, both x and y=3 then equation (1) may be rewritten as C.sub.3 =3C.sub.2 =3C.sub.1. In accordance with the teachings therein, the write efficiency may, for practical purposes, be raised to about 80%. This is done by tailoring the various capacitances in order to effectively alter the capacitance distribution ratio for both the read operation and the write/erase operations. Further, when both poly layers are driven together (the same voltage of the same polarity applied thereto), the induced voltage across the layer of tunnel oxide is reduced to about 20% of the applied voltage during the read operation.
The results sought in our prior application were achieved by tailoring the shape of the floating gate memory so that, at its narrowest portion, it is aligned with the channel region and also extends outwardly over the field oxide which is adjacent to and defines the channel region. Further, by tailoring the length (the shorter dimension) of both the program line and the word line, the overlap of the word line over the program line, as well as the thicknesses of the oxide therebetween, we are able to achieve the efficiencies sought. Accordingly, this corresponding application is incorporated herein in its entirety.